In this course, we will study the 8086 microprocessor, its features, and the difference between 8086 and 8085 microprocessors. So let us start.
What is the 8086 microprocessor?
It was the first 16-bit microprocessor built. It is an example of a complex instruction set computer(CISC). The 8086 microprocessor was first introduced in the year 1978.
- It supports pipelining which means it supports faster execution of the instructions.
- The 8086 consists of 20 address lines and 16 data lines. It can support up to 64k input/output ports.
- The registers in this microprocessor are 14-16 bits.
- It can access up to 220 memory locations.
- There are two modes of operations that can be performed- the minimum and maximum mode. The maximum mode is for the usage by the systems having multiprocessors and the minimum mode is for the systems having a single processor.
- It has a powerful instruction set that helps in making division and multiplication easy.
What are the features of the 8086 microprocessor?
- It consists of an instruction queue that is capable of storing 6 instruction bytes from the memory. And due to this property, the processing is fast.
- The microprocessor was the first 16-bit processor having 16-bit ALU. it consists of the 16-bit register, internal data bus, and 16-bit external data bus which helps in faster processing.
- There are 3 versions available of 8086 which depends upon the frequency of operation.
- There are two stages of pipelining that are used- the fetch stage and execute stage, which helps in improving the performance.
- It has a multiplexed address and data bus.
- To provide internal timing it requires a single-phase clock with a 33% duty cycle.
- The microprocessor is able to prefetch up to 6 instruction bytes from memory and can queue them in order to boost up the execution of the instruction.
- The instructions are executed in the execution stage.
What are the basic parts of 8086?
The Bus Interface Unit (BIU)
BIU performs the following functions-
- It generates the 20-bit physical address for accessing memory.
- Instructions are fetched from the memory.
- It transfers data between the memory and the I/O
- Maintains the 6-byte prefetch instruction queue.
There are 4 Segment registers in BUI. They are the Instruction Pointer, a prefetch queue, and an Address Generation Circuit.
Instruction Pointer (IP)
- It is a 16-bit register. It holds the offset of the next instructions in the Code Segment.
- It is incremented after every instruction byte is fetched.
- It gets a new value whenever a branch instruction occurs.
Code Segment register
It holds the base address for the Code Segment. All the programs are stored in the Code Segment and are accessed via the IP.
Data Segment register
It holds the base address for the Data Segment.
Stack Segment register
It holds the base address for the Stack Segment.
Extra Segment register
It holds the base address for the Extra Segment.
Address Generation Circuit
The BIU has a Physical Address Generation Circuit. The 20-bit physical address is being generated by using Segment and Offset addresses.
6 Byte Prefetch Queue
- It is a 6-byte queue (FIFO).
- Fetching the next instruction during the execution of the current instruction is called pipelining.
- Gets flushed whenever a branch instruction occurs.
The Execution Unit (EU)
- Fetches instructions from the Queue in BIU, decodes it, and then executes arithmetic and logic operations using the ALU.
- It Sends the control signals for internal data transfer operations within the microprocessor.
- It Sends the request signals to the BIU to access the external module.
- It operates with respect to T-states.
There are 16 general purpose registers AX, BX, CX, and DX. Store intermediate values during execution. Each of these has two 8 bit parts (higher and lower).
- AX register: It holds operands and results during multiplication and division operations. Also an accumulator during String operations.
- BX register: It holds the memory address (offset address) in indirect addressing modes.
- CX register: It holds the count for instructions like a loop, rotates, shifts, and string operations.
- DX register: It is used along with AX to hold 32-bit values during multiplication and division operations.
Arithmetic Logic Unit (16 bit)
Performs 8 and 16-bit arithmetic and logic operations.
Special purpose registers (16-bit)
- Stack Pointer: Points to Stack top. The stack is in Stack Segment, used during instructions like PUSH, POP, CALL, RET, etc.
- Base Pointer: It can hold the offset address of any location in the stack segment and is used to access random locations of the stack.
- Source Index: It holds an offset address in the Data Segment during string operations.
- Destination Index: It holds an offset address in the Extra Segment during string operations.
Instruction Register and Instruction Decoder
The execution unit fetches an opcode from the queue into the instruction register. The instruction decoder decodes it and then sends the information to the control circuit for its execution.
There are 9 flags that help change or recognize the state of the microprocessor.
6 Status flags:
- Carry flag (CF)
- Parity flag (PF)
- Auxiliary carry flag (AF)
- Zero flags (Z)
- Sign flag (S)
- Overflow flag (O)
3 Control flags
- Trap flag(TF)
- Interrupt flag(IF)
- Direction flag(DF)
Difference between 8085 microprocessors and 8086 microprocessors
|Here the data bus is of 8 bits
||Here the data bus is of 16 bits
|Here the address bus is of 16 bits
||Here the address bus is of 20 bits
|Its memory capacity is 64 KB
||Its memory capacity is 1MB
|We can perform up to 256 number operations
||We can perform up to 65536 number operations
|The operational frequency is 3.2Hz
||The operational frequencies are 8Hz, 10Hz and 5Hz
|There is only one mode of operation in 8085 microprocessor
||There are two modes of operations in 8086. They are minimum and maximum mode
|The multiplication and division operation can not be performed in it
||We can perform multiplication and division operation in it
|Pipelining and instruction queue is not supported in 8085
||8086 supports pipelining and instruction queue